Verification of Linearizability and Lock-freedom

Date: Thursday, February 14, 2013
Speaker: Gerhard Schelhorn
Venue: IST Austria

With multi-core processors now in common use,implementations of data structures which allow forefficient, concurrent access by many processeshave become an important basic building block for applications.The talk will introduce linearizability and lock-freedom asthe standard safety and liveness criteria for concurrentdata structures. The first part of the talk then will present asound and complete proof technique for linearizability basedon backward simulations.The second half of the talk will sketch a temporal logic frameworkimplemented in the interactive theorem prover KIV, that has been usedto verify both linearizability and lock-freedom for several casestudies.

Posted in RiSE Seminar