Analysis of fault-tolerant distributed on-chip algorithms

Date: Thursday, November 04, 2010
Speaker: Matthias Fuegger
Venue: IST Austria

For Very Large Scale Integrated (VLSI) Circuits intended to be used inhighly reliable applications, formal specification and analysis ismandatory. Two trends in VLSI design favour a modeling approachanalogous to that used for distributed systems: (i) noticeablecommunication delays between circuit components and (ii) increasingfailure rates caused by wear-out and particle hits in circuits withever decreasing feature sizes. Despite these striking similarities,specifying and analyzing circuits by means of classic distributedsystem models is either overly lengthy or not possible. To overcomethese limitations a new modeling and analysis framework tied to thepeculiarities of fault-tolerant on-chip algorithms ispresented.

The capabilities of this framework are then illustrated by applying it(i) to analyze and prove correct a fault-tolerant on-chip tickgeneration algorithm and (ii) to prove the impossibility of solvingthe short-pulse filter problem with purely digital and statelessmodules only.

Posted in RiSE Seminar