Christian Herrera

Date: 16:00, Tuesday, November 24, 2015
Speaker: Christian Herrera
Venue: IST Austria
Notes:

Time: 16:00, Day: Tuesday

Quasi-equal clock reduction for networks of timed automata
replaces clocks in equivalence classes by representative clocks. An exist-
ing approach which reduces quasi-equal clocks and does not constrain
the support of properties of networks, yields significant reductions of the
overall verification time of properties. However, this approach requires
strong assumptions on networks in order to soundly apply the reduc-
tion of clocks. In this work we propose a transformation which does not
require assumptions on networks, and does not constrain the support
of properties of networks. We demonstrate that the cost of verifying
properties is much lower in transformed networks than in their original
counterparts with quasi-equal clocks.

Posted in RiSE Seminar